Document
Personal Portfolio
Author
Sathya Mitiran
Field
Computer Engineering
Status
Actively Maintained
Machine Learning Intern — Capital Engineering Consultancy
Undergraduate Researcher — UIUC

Sathya Mitiran Jayaprakash Suvithaa

Computer Engineering — University of Illinois Urbana-Champaign

Sathya Mitiran Jayaprakash Suvithaa

I move across abstraction layers, hardware, software, and markets. Some days that is RTL or a VLSI layout, other days it is embedded systems, machine learning, or other data work, and other days it is figuring out how a financial system actually behaves.

assign OPEN_TO_WORK = 1'b1; // internships 2026–27 · full-time 2027+
View Projects Contact
Focus

Pin Configuration

SMJS COMPUTER ENGINEERING QFN-6 · REV C
1
RTL & Verification
SystemVerilog, self-checking testbenches, FPGA bring-up
 2
VLSI & Physical Design
Cadence Virtuoso, Innovus, VCS, Verdi, standard cell layout
 3
Computer Architecture
RISC-V, custom ISA and CPU builds
 4
GPU Architecture
CUDA, parallel programming, inference on raw hardware
 5
Embedded & Firmware
C/C++, STM32, real-time systems close to the hardware
 6
Data & Software
Python, analytics, full-stack apps behind all of it
Fig. 2 — Pin configuration, top view. 6-pin package.
P1
RTL & Verification
SystemVerilog, self-checking testbenches, FPGA bring-up
P2
VLSI & Physical Design
Cadence Virtuoso, Innovus, VCS, Verdi, standard cell layout
P3
Computer Architecture
RISC-V, custom ISA and CPU builds
P4
GPU Architecture
CUDA, parallel programming, inference on raw hardware
P5
Embedded & Firmware
C/C++, STM32, real-time systems close to the hardware
P6
Data & Software
Python, analytics, full-stack apps behind all of it
Experience

Experience

6 channels captured — Jun 2022 to present

LASSI
ML Intern
Undergrad Research
VC Analytics Intern
Repair Technician
Networking Intern
20222023202420252026
Aug 2026 — Present
Software Development Team Member
Laboratory for Advanced Space Systems at Illinois (LASSI)
Jul 2026 — Present
Machine Learning Intern
Capital Engineering Consultancy
Oct 2025 — Present
Undergraduate Researcher
University of Illinois Urbana-Champaign · Champaign, IL
Building agentic AI tooling for FPGA design optimization. See the project →
Aug 2024 — Oct 2024
Corporate VC & Business Analyst
HP Tech Ventures
Jun 2023 — Jul 2024
Computer Repair Technician
DPC Computer Repair · Naperville, IL
Jun 2022 — Jul 2022
Computer Networking Intern
Capital Engineering Consultancy
Featured — Undergraduate Research
Agentic-AI Framework for Post-Route Optimization of FPGA Designs
Undergraduate Researcher, UIUC — advised by David Lariviere
Presented — UIUC Future of Fintech Expo Displayed — STAC Conference Recognized by STAC's CEO
“I came away impressed by the technical depth, creativity, and practical relevance of the work the team produced.”— Jack Gidding, CEO, STAC · LinkedIn recommendation ↗
Input DCPFmax = 395 MHz
Vivado MeasuresWNS · route status
fanout · timing
AI Agentanalyze design →
formulate strategy →
apply optimizations
RapidWright Editsnets · cells
pblocks · DCPs
feedback loop — keep changes only if WNS improves
Output DCPFmax = 500 MHz

FPGA timing closure after place-and-route is still mostly manual: read the timing report, guess a strategy, re-run, repeat. This framework puts an AI agent in that loop. A Python wrapper around RapidWright reads and edits Vivado Design Checkpoints directly, and Vivado / RapidWright MCP servers let the agent inspect timing reports and act on them, choosing between high-fanout net splitting, pblock-based placement, and physical optimization until slack recovers.

31
DCPs tested
+0.34 ns
avg WNS gain
81%
timing closed
PythonRapidWrightVivadoMCPFPGALLM Agents
Projects

Projects

13 shipped · 1 featured · 0 abandoned

Contact

Contact

// end of document — corrections, questions, and offers all welcome

Direct
sathyamitiran@gmail.com
Elsewhere
LinkedIn GitHub Resume

Reach out about hardware, software, research, internships, or full-time roles.